The present invention regards a process for manufacturing an electronic device comprising nonvolatile memory cells with dimensional control of the floating gate regions.
Devices using nonvolatile memories of the EEPROM type, such as smart cards, complex microcontrollers and mass storage devices, which require programmability of the individual byte, call for increasingly higher levels of performance and reliability.
In practice, from the technological standpoint, it is necessary to get high levels of performance (i.e., increasingly thinner tunnel oxides, ever more reduced programming voltages, increasingly greater cell current driving capability, etc.) to coexist with high reliability. One hundred thousand programming cycles and retention of the charge stored for at least ten years are by now considered the minimum requisites for the acceptance of this type of product on the market.
On the basis of the above, new manufacturing processes and new geometries are needed that are able to eliminate some of the critical aspects typical of memories, thus increasing their intrinsic reliability without reducing their performance, both for xe2x80x9cembeddedxe2x80x9d applications (i.e., when the memory cells are associated to special electronic devices) and for stand alone applications (i.e., when the device is merely a nonvolatile memory).
In particular, European Patent Application No. 99830347.3 filed on Apr. 6, 1999 describes a process for manufacturing a memory cell wherein the floating gate mask has an opening with an internal delimiting side extending at a preset distance from a corresponding external delimiting side, so that the floating gate region forms internally a hole, and the tunnel area is defined in length by the floating gate mask alone. The hole is filled with a dielectric material layer; then, the surface of the floating gate region is planarized, and an insulating region of dielectric material is formed.
Next, a second polycrystalline silicon layer (poly2) is deposited and shaped so as to form a control gate region and, at the same time, a selection transistor gate region. Finally, conductive regions are formed in the active area.
This process is advantageous in that a precise dimensional control of the tunnel region may be obtained. However, it poses the problem that the height difference during the definition of structures belonging to the same layer, such as the control gate of the memory transistor and the gate region of the selection transistor, requires critical and sophisticated etching processes to eliminate possible residual material that occurs in complex geometries.
The disclosed embodiments of the present invention provide a manufacturing process that enables elimination of the critical aspects when defining a second polysilicon layer.
According to embodiments of the present invention, a process for manufacturing an electronic device comprising EEPROM memory cells, and the thus obtained electronic device, are provided. The process includes forming a first dielectric material layer on top of a semiconductor material substrate that includes a tunnel area; simultaneously forming a floating gate region on top of the first dielectric material layer to partially overlie the tunnel region and forming a lower gate portion on top of the first dielectric material layer in a position adjacent to and at a distance from the floating gate region, which includes the steps of depositing a first semiconductor material layer above the first dielectric material layer and the tunnel area and selectively removing the first semiconductor material layer externally to the floating gate region and the lower gate portion and inside the floating gate region to form a hole therein; forming an insulating structure surrounding the floating gate region, including coating the hole with an insulating material; simultaneously forming a control gate region on top of the insulating structure and an upper gate portion on top of the lower gate portion; and forming conductive regions in the semiconductor material substrate.